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Carry Look Ahead Adder- In  Ripple Carry Adder , each full adder has to wait for its carry-in from its previous stage full adder to start its operation which causes an unnecessary delay. Carry Look Ahead Adder is an improved version of the ripple carry adder which generates the carry-in of each full adder simultaneously without causing any delay. Logic Diagram for Carry Look Ahead Adder- Working of Carry Look Ahead Adder- The working of carry look ahead adder is based on the principle that the carry-in of any stage full adder is independent of the carry bits generated during intermediate stages and is only dependent of the following two parameters- Bits being added in the previous stages Carry provided in the beginning Since, the above two parameters are always known, the carry-in of any stage full adder can be evaluated at any instant of time. Thus, a full adder need not wait until its carry-in is generated by its previous stage full adder. Adv

  Introduction to combinational circuit::- Combinational circuit is a circuit in which we combine the different gates in the circuit, for example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational circuits are following − The output of combinational circuit at any instant of time, depends only on the levels present at input terminals. The combinational circuit do not use any memory. The previous state of input does not have any effect on the present state of the circuit. A combinational circuit can have an n number of inputs and m number of outputs. Block diagram We're going to elaborate few important combinational circuits as follows. Half Adder Half adder is a combinational logic circuit with two inputs and two outputs. The half adder circuit is designed to add two single bit binary number A and B. It is the basic building block for addition of two  single  bit numbers. This circuit has two outputs  carry and  sum

Arithmetic and Logic Unit (ALU): Arithmetic and Logic Unit is a like a calculator to a computer. ALU performs all arithmetic operations along with decision making functions. In modern CPU or Microprocessors, there can be more than one integrated ALU to speed up arithmetical and logical operations, such as; integer unit, floating point unit etc. Organization of ALU: Various circuits are required to process data or perform arithmetical operations which are connected to microprocessor's ALU. Accumulator and Data Buffer stores data temporarily. These data are processed as per control instructions to solve problems. Such problems are addition, multiplication etc. Functions of ALU: Functions of ALU or Arithmetic & Logic Unit can be categorized into following 3 categories 1. Arithmetic Operations: Additions, multiplications etc. are example of arithmetic operations. Finding greater than or smaller than or equality between two numbers by using subtraction  is

Cache Memory in Computer Organization Cache Memory  is a special very high-speed memory. It is used to speed up and synchronizing with high-speed CPU. Cache memory is costlier than main memory or disk memory but economical than CPU registers. Cache memory is an extremely fast memory type that acts as a buffer between RAM and the CPU. It holds frequently requested data and instructions so that they are immediately available to the CPU when needed. Cache memory is used to reduce the average time to access data from the Main memory. The cache is a smaller and faster memory which stores copies of the data from frequently used main memory locations. There are various different independent caches in a CPU, which stored instruction and data. Levels of memory: Level 1 or Register – It is a type of memory in which data is stored and accepted that are immediately stored in CPU. Most commonly used register is accumulator, Program counter, address register etc. Level 2 or Cac

Memory Hierarchy Design and its Characteristics In the Computer System Design, Memory Hierarchy is an enhancement to organize the memory such that it can minimize the access time. The Memory Hierarchy was developed based on a program behavior known as locality of references.The figure below clearly demonstrates the different levels of memory hierarchy : This Memory Hierarchy Design is divided into 2 main types: External Memory or Secondary Memory – Comprising of Magnetic Disk, Optical Disk, Magnetic Tape i.e. peripheral storage devices which are accessible by the processor via I/O Module. Internal Memory or Primary Memory – Comprising of Main Memory, Cache Memory & CPU registers. This is directly accessible by the processor. We can infer the following characteristics of Memory Hierarchy Design from above figure: Capacity: It is the global volume of information the memory can store. As we move from top to bottom in the Hierarchy, the capacity increases. Acces

Redundancy :- Instead of repeating the entire data stream, a shorter group of bits may be appended to the end of each unit. This technique is called Redundancy because the extra bit are redundant to the information. They are discarded as soon as the accuracy of the transmission has been determined. These are the basically four types of redundancy check. 1. VRC (vertical redundancy check) 2. LRC (longitudinal redundancy check) 3. CRC ( cyclical redundancy check) Vertical redundancy check:- It is also known as parity check. It is least expensive mechanism for error detection. In this technique, the redundant bit called parity bit is appended to every data unit so that the total number 1s in the unit becomes even. Features:- VRC can detect all single bit errors . It can detect burst errors if the total number of  errors in each data unit is odd. VRC can not detect erros where the total number of bits changed is even. Drawback:- This

      Error detection techniques 1. Simple Parity check  Blocks of data from the source are subjected to a check bit or parity bit generator form, where a parity of : 1 is added to the block if it contains odd number of 1’s, and 0 is added if it contains even number of 1’s This scheme makes the total number of 1’s even, that is why it is called even parity checking. 2. Two-dimensional Parity check Parity check bits are calculated for each row, which is equivalent to a simple parity check bit. Parity check bits are also calculated for all columns, then both are sent along with the data. At the receiving end these are compared with the parity bits calculated on the received data. 3. Checksum In checksum error detection scheme, the data is divided into k segments each of m bits. In the sender’s end the segments are added using 1’s complement arithmetic to get the sum. The sum is complemented to get the checksum. The checksum segment is sent along with the data segme

Error Detection in Computer Networks Error A condition when the receiver’s information does not matches with the sender’s information. During transmission, digital signals suffer from noise that can introduce errors in the binary bits travelling from sender to receiver. That means a 0 bit may change to 1 or a 1 bit may change to 0. Error Detecting Codes (Implemented either at Data link layer or Transport Layer of OSI Model) Whenever a message is transmitted, it may get scrambled by noise or data may get corrupted. To avoid this, we use error-detecting codes which are additional data added to a given digital message to help us detect if any error has occurred during transmission of the message. Basic approach used for error detection is the use of redundancy bits, where additional bits are added to facilitate detection of errors. Some popular techniques for error detection are: 1. Simple Parity check 2. Two-dimensional Parity check 3. Checksum 4. Cyclic redundancy

Basics of Computer Networking Open system: A system which is connected to the network and is ready for communication. Closed system: A system which is not connected to the network and can’t be communicated with. Computer Network:  It is the interconnection of multiple devices, generally termed as Hosts connected using multiple paths for the purpose of sending/receiving data or media. There are also multiple devices or mediums which helps in the communication between two different devices which are known as  Network devices . Ex: Router, Switch, Hub, Bridge. The layout pattern using each device are interconnected is called as network topology such as bus ,star ,mesh, ring, daisy chain.

      Link state routing algorithm Link State Routing – Link state routing is the second family of routing protocols. While distance vector routers use a distributed algorithm to compute their routing tables, link-state routing uses link-state routers to exchange messages that allow each router to learn the entire network topology. Based on this learned topology, each router is then able to compute its routing table by using a shortest path computation. Features of link state routing protocols – Link state packet –  A small packet that contains routing information. Link state database –  A collection information gathered from link state packet. Shortest path first algorithm (Dijkstra algorithm) –  A calculation performed on the database results into shortest path Routing table –  A list of known paths and interfaces. Calculation of shortest path – To find shortest path, each node need to run the famous  Dijkstra algorithm . This famous algorithm uses the following step

    Distance vector routing protocols A distance vector routing protocol in data network determines the best route for data packet based on distance.   Distance vector routing protocol measure the distance by the number of routers a packet has to pass, one routers counts as one hop.   Distance vector routing protocols use the Bellmen- ford algorithm and fork - fulkerson algorithm to calculate the best route.   Distance vector routing protocol requires that a router inform it's neighbours of topology changes periodically.  Historically known as the old ARPANATE routing algorithm known as bellmen-ford algorithm.  Distance vector routing algorithm is distributed algorithm .   This routing algorithm is a iteration algorithm. Whenever a packet comes to router the neighbouring router will give the vector table and a new vector table is created at that router.          Distance Vector Routing Algorithm- Distance Vector Routing is a dynamic routing algorithm. I